1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an improvement of electrodes and wiring of a semiconductor device and also a method of the electrodes and the wiring.
2. Description of the Related Art
The major sections of computers and communication apparatuses incorporate large-scale integrated circuits (LSIs), each comprising many transistors and many resistors which are electrically connected, forming electric circuits on a single semiconductor chip. The operating efficiency of a computer or a communication apparatus largely depends on the operating efficiencies of the LSIs used in the computer or the apparatus. The operating efficiency of each LSI can be enhanced by increasing the integration density of the LSI--that is, by making the elements constituting the LSI smaller.
In recent years, the sizes of LSI elements have been reduced. Thanks to the size-reduction of LSI elements, the integration densities of LSIs have been increased and the operating speeds thereof have been raised. The higher the speed of each LSI element, the more greatly it is restricted by the RC delay of the gate electrode or gate wiring of the LSI element.
The RC delay can be decreased by increasing the thickness of the gate electrode or the gate wiring, thereby decreasing the resistance of the electrode or wiring, even if the material of the gate electrode or the gate wiring is not changed. An increase in the thickness of the gate electrode or wiring is, however, problematical in view of the process of forming the gate electrode or the gate wiring. In the case of the gate electrode, it is desired that its aspect ratio (i.e., the ratio of the gate height to the gate length) should not greatly exceed the value of 1.
There is available a method of decreasing the resistance of the gate electrode without increasing the thickness of the electrode. The method is to form the electrode of a two-layer film consisting of a polycrystalline silicon layer and a refractory metal silicide layer. If this method is employed, the threshold voltage of the LSI element having the gate electrode can be controlled by the method used in the conventional process of forming silicon gates. In addition, such a two-layer film can be easily formed by the conventional process of forming silicon gates since most refractory metal silicides have high thermal resistance.
If a MOSFET having a gate length of, for example, 0.3 .mu.m or less has its gate electrode made of such a two-layer film, the thickness of the refractory metal silicide layer is limited to about 100 to 200 nm. In this case, the sheet resistance of the gate electrode layer can be decreased to only about a few tens of ohms per unit area.
Assume that a gate electrode having a width of 0.25 .mu.m and a sheet resistance of about 1.OMEGA./.quadrature. has been formed of a two-layer film which consists of a polycrystalline silicon layer and a refractory metal silicide layer. Then, the refractory metal silicide layer has a thickness of about 1 .mu.m. Inevitably, this gate electrode has an aspect ratio as high as 4 to 5. It is therefore difficult to pattern the gate electrode and to form an inter-layer insulating film on the patterned gate electrode.
It has been proposed that the small gate electrode of a MOSFET be made of a two-layer film consisting of a layer of a polycrystalline silicon layer and a refractory metal layer (e.g., a tungsten or molybdenum layer) which has a lower resistance than refractory metal silicides but sufficient thermal resistance, so that the gate may have a thickness of 100 nm and a sheet resistance of a few ohms per unit area. If the refractory metal layer is made of tungsten, tungsten reacts with silicon at a temperature of about 600.degree. C., forming tungsten silicide, though it is said to hardly react with silicon. As a consequence, the resistance of gate electrode increases.
To prevent the reaction of tungsten with silicon, a reaction-inhibiting film may be interposed between a polycrystalline silicon layer and a refractory metal layer. Jpn. Pat Appln. KOKAI Publication No. 60-195975, for example, discloses that a silicon nitride film effectively prevents a molybdenum layer from reacting with a polycrystalline silicon layer. The publication teaches that the silicon nitride film should desirably have a thickness ranging from 1 nm to 5 nm in order to allow a tunnel current to flow between the molybdenum layer and the polycrystalline silicon layer.
As the element size is reduced, it becomes more difficult to control the size of any part of the element and to provide the part in a desired shape. The size of the gate electrode of a MOSFET greatly affect the operating efficiency of the MOSFET. Hence, it is demanded that process techniques be developed for providing a gate electrode whose width (gate length) is little different from the design size.
A two-layer film consisting of a layer of a polycrystalline silicon layer and a tungsten layer (a refractory metal layer) may be dry-etched to form the gate electrode of a MOSFET. If this is the case, the two-layer film is etched for a time long enough to etch away a film which has the same structure but is a thicker by .alpha.. The process for etching a film of the extra thickness is known as "over etching." The over etching must be performed because a two-layer film generally has at least one portion thicker than the other portions. Unless the film is etched even after the other portions have been etched, its thicker portion cannot be etched completely.
Here arises a problem. The tungsten layer is etched more slowly than the polycrystalline silicon layer. The polycrystalline silicon layer is greatly etched when the tungsten layer is over-etched. Assume that the two-layer film is dry-etched by, for example, RIE (Reactive Ion Etching) in which SF.sub.6 gas and Cl.sub.2 gas are applied to the two-layer film at flow rates of 40 SCCM and 10 SCCM, respectively, in an atmosphere at a pressure of 10 mTorr, a high-frequency voltage of 0.7 W/cm.sup.2 is applied to the two-layer film, and the two-layer film is maintained at 70.degree. C. Then, the tungsten layer is etched at the rate of about 180 nm/min, whereas the polycrystalline silicon layer beneath the tungsten layer is etched at the rate of about 700 nm/min. The ratio of the etching rate of the tungsten layer to that of the polycrystalline silicon is inevitably as low as about 0.3.
Hence, even of the two-layer film which consists of a layer of a polycrystalline silicon layer and a tungsten layer (a refractory metal layer) is dry-etched, it is impossible to form a patterned gate electrode which has a desired shape.